This invention relates to an analog-to-digital converter, and more particularly to an analog-to-digital converter capable of automatically performing the zero adjustment and the full scale adjustment.
An analog-to-digital converter (which is hereinafter abbreviated to "A-D converter") of dual slope type (for example, shown in U.S. Pat. No. 3,316,547) is conventionally known as among the A-D converters. In principle, this type of A-D converter comprises, as shown in FIG. 1, a D.C. amplifier 1, an integrator composed of an input resistor R and an integration capacitor C, a comparator 2, and a change-over switch 3, and is so constructed that an input voltage V.sub.S and a reference voltage -V.sub.R being applied to an input terminal 4 may properly be changed over by the change-over switch 3 to determine a digital amount of the input voltage V.sub.S. As shown in FIG. 2, the positive input voltage V.sub.S is first applied to the terminal 4 for a specified length of time T.sub.1 to decrease the output voltage V.sub.O of the D.C. amplifier applied to the positive input terminal of the comparator 2. Then, a voltage being applied to the input terminal 4 is changed over to the negative reference voltage -V.sub.R to increase the above output voltage V.sub. 0, and a length of time T.sub.2 required until an output is produced from the comparator 2 after said output voltage V.sub.0 reaches the reference level V.sub.C applied to the negative input terminal of the comparator 2 is measured. If, at this time, the potential of the inversion input terminal of the D.C. amplifier 1 is zero, that is to say, if there is no offset, the following relation will be established. ##EQU1## The T.sub.1 and T.sub.2 are determined by counting the number of clock pulses by, for example, counters. Accordingly, the ratio of the input V.sub.S to the reference voltage V.sub.R, (V.sub.S /V.sub.R), is determined as the ratio of the count during the length of time T.sub.2 to the count during the length of time T.sub.1 (T.sub.2 /T.sub.1)(= digital amount).
In the case where there is no offset at the D.C. amplifier 1 as mentioned above, an exact measurement can be made of the input voltage V.sub.S. Generally, however, the above equation (1) does not hold true due to the offset of the D.C. amplifier 1. That is, if the offset voltage is represented by .DELTA.V, ##EQU2## Accordingly, an error attributed to the offset voltage .DELTA.V is produced. Accordingly, the above input voltage V.sub.S was usually measured after the operating voltage of the D.C. amplifier was manually adjusted so as to compensate the offset voltage .DELTA.V. Since, however, the .DELTA.V is subjected to change with time or with temperature, an exact measurement would require the zero adjustment or full scale adjustment each time the measurement is made.
In order to correct such errors originating in the .DELTA.V, such a method as shown in FIG. 3 is conventionally proposed. Parts and sections of FIG. 3 the same as those of FIG. 1 are denoted by the same reference numerals. In the arrangement of FIG. 3, the output end of the D.C. amplifier 1 is grounded through a switch 5 and a capacitor 6, and a connection point between the switch 5 and the capacitor 6 is connected to the gate electrode of an FET 7, and the source electrode of the FET 7 is connected to a terminal 8 of the change-over switch 3, thus to construct an A-D converter. The source of the FET 7 is connected to a power source of -B through a resistor, while the drain thereof is connected to a power source of +B.
In this circuit arrangement, the common terminal 4 in the change-over switch 3 is first connected to the terminal 8 and simultaneously the switch 5 is closed. As a result, a current determined by .DELTA.V/R flows in the resistor R to charge the capacitor C of the integrator. When the circuit has been brought to a stationary condition, the voltage at the inversion input terminal of the D.C. amplifier 1 and the source voltage of the FET 7 are equalized and current ceases to flow in the resistor R. At this time, the source voltage of the FET 7 relative to the earth potential is -.DELTA.V, while the voltage across the terminals of the capacitor 6 has such a level as permits the source voltage of the FET 7 relative to the earth potential to be -.DELTA.V.
When, at this time, the switch 5 is opened and the change-over switch 3 is so changed over as to connect the common terminal 4 to a terminal supplied with the input voltage V.sub.S, a voltage of V.sub.S -.DELTA.V is integrated. When, after this integration is made for a length of time T.sub.1, the changeover switch 3 is so changed over as to connect the terminal 10 to the terminal 4, with the switch 5 kept open, a voltage of -V.sub.R -.DELTA.V is integrated. When it is assumed that a length of time required from the change-over of the switch until the integration output goes across the reference level (0 level) is represented by T.sub.2, the following equation is established. EQU (V.sub.S - .DELTA.V + .DELTA.V)T.sub.1 + (-V.sub.R - .DELTA.V + .DELTA.V)T.sub.2 = 0
accordingly, V.sub.S T.sub.1 = V.sub.R T.sub.2. That is to say, ##EQU3##
Namely, the method of FIG. 3 consists in connecting the terminal 4 to the terminal 8 thereby to produce at the inversion input terminal of D.C. amplifier 1 beforehand a voltage -.DELTA.V (as expressed in terms of analog value) whose polarity is opposite to that of the offset voltage .DELTA.V of the D.C. amplifier 1, and upon actual measurement adding this voltage -.DELTA.V to the V.sub.S and -V.sub.R thereby to correct errors as resulting from the .DELTA.V.
According to the above-mentioned method, therefore, the zero adjustment and the full scale adjustment can be carried out by closing the switch 5 for each measurement to obtain beforehand a corresponding voltage being added to the offset voltage.
However, the above-mentioned conventional A-D converter has the following drawbacks.
First, where an attempt is made to effect the converter miniaturization by converting a circuit for effecting the error correction into an integrated circuit form (IC form), the existence of the capacitor 6 prevents a completion of said circuit into an IC form. Second, in order to produce a voltage of -.DELTA.V there are required the switch 5 and the capacitor 6, which should however be extremely small in terms of current orrect leak. That is, if there occurs a current leak, variations will take place in the analog level of -.DELTA.V during the period for actual measurement, leading to a failure to perform an exact A-D conversion. Third, where it is desired to produce beforehand a voltage having a specified level of -.DELTA.V, stabilization of the circuit under a condition of the power source being turned ON must be waited, and therefore a long time is required until an actual measurement becomes possible after the power source is turned ON. Fourth, where the input voltage V.sub.S is 0, a dual slope is not produced. It is therefore impossible to perform an A-D conversion in the case of the input voltage V.sub.S = 0.